In general, gate arrays have a row of cells which are a collection of basic cells each comprising a plurality of insulated gate field effect transistors (hereinafter referred to as MIS's) and a plurality of input/output cells (I/O cells), and a large scale logic circuit and the like can be configured as desired by simply providing a wiring channel and the like on the chid with a power line and a signal line depending on user specification.
Various types of cell configuration have been proposed as a library for the input/output cells (I/O cells), and they are all I/O buffer based configuration, in order for the output transistor of I/O cells to be compatible with an external TTL, it needs to have capability of allowing a sink current of 0.4 mA cells at a potential difference of 0.4 V, for example. The value of the output current can be varied by connecting a single output signal line from a dedicated logic circuit comprising internal basic cells to a plurality of I/O cells by changing the wiring layout. However, once it has been incorporated into a chip-packaged electronic circuit after the wiring process has been completed, the value of the output current is consistently fixed and, therefore, there is no flexibility to make it possible to save power consumption depending on changes in system environment or to perform high power driving when required. Though the value of the output current may be varied to some extent by adjusting the voltage level of the external power source, it is not preferred to vary the level of the power source voltage because it has influence on other elements. In recent years, there has been a need for semiconductor integrated circuits which make it possible to actively variably adjust a predetermined value of an output current in the system environment after chip-packaging.
Considering the above-mentioned need, the present invention realizes master slice semiconductor integrated circuits in which the value of the output current can be variably controlled internally or externally.